1. Field of the Invention
The invention relates in general to the fabrication of semiconductor memory devices, and more particularly to the fabrication of DRAM cells which include two stacked storage capacitors implemented with a common trench for each pair of memory cells.
2. Description of the Related Art
In this electronic information age, DRAMs are so widely used in integrated circuits that doing without them is unthinkable. The structure of earlier DRAM cells consists of three transistors linked together. However, with rapid improvements in semiconductor technology, most memory cells now consist of just one pass transistor together with a storage capacitor, in order to meet the demand for high level integration through a reduction in component dimensions. In general, the source terminal of the pass transistor is connected to a bit line and the drain terminal is connected to the storage electrode of a storage capacitor, while the gate terminal is connected to a word line. The opposed electrode of the storage capacitor is connected to a fixed voltage source, and the gap between the storage electrode and the opposed electrode is filled by a dielectric layer. As persons familiar with the technology will understand, the storage capacitor is a device for storing charge representing data, and therefore should possess sufficiently high capacitance that the number of refreshes necessary to avoid data loss through charge leakage is minimized.
In the conventional process for manufacturing a 1 MB DRAM, for example, two dimensional capacitor components of a so-called planar-type capacitor are formed above the surface of a silicon substrate. However, the storage capacitor of the planar-type must occupy a considerable amount of surface area in the substrate in order to provide sufficient capacitance for operation, and as such, cannot meet the stringent processing demands for an ever increasing level of DRAM component integration. Thus, for highly integrated DRAMs, such as those having a memory capacity greater than 4 MB, it is necessary to utilize the third dimension in constructing the capacitor as well. There are many three-dimensional capacitor structures in use, and they can be classified roughly into two types, the so-called "stack type" and the so-called "trench type." Yet, no matter how much these known capacitor structures increase the capacitance, each capacitor component still must occupy a certain substrate area, and this sets a limit on the degree of miniaturization possible.
FIG. 1 is a circuit diagram of a pair of memory cells of a conventional trench type capacitor DRAM. The gate terminal 10 of a pass transistor T.sub.1 is connected to a word line WL, the source region 14 is connected to a bit line BL.sub.1, the drain region 16 is connected to the storage electrode 18 of a trench type capacitor C.sub.1 , and the storage electrode 18 is surrounded by the opposed electrode 20 of the storage capacitor C.sub.1 . Similarly, the gate terminal 10 of another pass transistor T.sub.2 is connected to the word line WL, source region 14 is connected to another bit line BL.sub.2, and drain region 16 is connected to the storage electrode 18 of another trench type capacitor C.sub.2. An insulating layer 22 is also formed in between the two storage capacitors C.sub.1 and C.sub.2 to separate them. Each capacitor component of the aforementioned conventional trench type capacitor structure occupies a fixed amount of substrate area. The insulating layer also occupies a certain additional amount of substrate area, further limiting the amount of miniaturization possible.
Considering this problem, a double stacked trench capacitor DRAM structure and manufacturing method have been suggested by the present inventor, as disclosed in U.S. Pat. No. 5,354,704. Its main characteristic lies in using the same trench to house two storage capacitors, with one capacitor stacked on top of another, and each of the two capacitors leading to a respective memory cell, thereby enabling a reduction in the substrate area requirement for the storage capacitors. To clarify the structural connection and operation of this device, reference is made to FIG. 2 and FIG. 3. FIG. 2 is a circuit diagram of a pair of memory cells of the double stacked trench capacitor DRAM and FIG. 3 is a cross-sectional view of this DRAM component structure. Here, as in the device of FIG. 1, the gate terminals 10 of both pass transistors T.sub.1 and T.sub.2 are connected to a word line WL, and their source regions 14 are respectively connected separately to bit lines BL.sub.1 and BL.sub.2. Storage capacitors for the memory cells are formed stacked one on top of another inside a common trench 25. The gap between the storage electrode 18a and opposed electrode 20 is filled by a layer of dielectric (not shown in the figure) to form a storage capacitor which is electrically coupled to the drain region 16 of pass transistor T.sub.1. Similarly, the gap between the storage electrode 18b and opposed electrode 20 is filled by a layer of dielectric (not shown in the figure) to form another storage capacitor that is electrically coupled to the drain region 16 of pass transistor T.sub.2. Insulating layer 23 is used to separate the capacitors inside the trench from the substrate.
Due to the stacked structure of two capacitors inside a common trench in the double stacked trench capacitor DRAM, two memory cells can use the same piece of storage capacitor area and therefore substantially increase the level of component integration. Further, the insulating layer 22 separating the storage capacitors shown in FIG. 1 can be omitted freeing additional surface area on the substrate. However, as shown in FIGS. 2 and 3, to create two capacitors with equal capacitance, storage electrode 18b has to extend a certain distance above the substrate in order to have the same area as that of the storage electrode 18a. Because of this, the inventor realized improvements could still be made in the structure, as well as the manufacturing process of such a component, to reduce the substrate area used and thereby lead to a further increase in the level of component integration.